1. Technical Field
The present invention relates generally to an improved apparatus and method for testing a system-on-a-chip. More specifically, the present invention is directed to an apparatus and method for testing sub-systems of a system-on-a-chip model using a configurable, previously verified, system-on-a-chip model as an external model in a simulation environment.
2. Description of Related Art
The complexity and sophistication of present-day integrated circuit (IC) chips has advanced significantly over those of early chip designs. Where formerly a chip might embody relatively simple electronic logic blocks effected by interconnections between logic gates, advanced semiconductor manufacturing technique have resulted in the ability to design silicon chips having millions of transistors available that permit different types of functions to be placed on the same chip. Thus, a complete system including micro-processors, memory, analog and power, etc. can be built on a single chip. Currently, chips can include combinations of complex, 30, modularized IC designs often called “cores” which together constitute an entire “system-on-a-chip,” or SoC. The key concept in SoC design is that a chip can be constructed rapidly using third-party and internal intellectual property (IP), i.e. pre-designed behavior or physical descriptions of a standard component.
In general, IC chip development includes a design phase and a verification phase for determining whether a design works as expected. The verification phase has moved increasingly toward a software simulation approach to avoid the costs of first implementing designs in hardware to verify them.
Typically, in verifying a design, a simulator is used. Here, “simulator” refers to specialized software whose functions include accepting software written in a hardware description language (HDL), such as Verilog or VHDL, for example, which models a circuit design (for example, a core as describe above), and using the model to simulate the response of the design to stimuli which are applied by a test case to determine whether the design functions as expected. The results are observed and used to debug the design.
In order to achieve acceptably bug-free designs, verification software must be developed for applying a number of test cases sufficient to fully exercise the design in simulation. In the case of SoC designs, the functioning of both the individual cores as they are developed, and of the cores interconnected as a system must be verified. Simulation which includes processor cores tends to require an inordinate amount of time and computing resources largely because the processor core is usually the most complex piece of circuitry on the chip and interacts with many other cores on the SoC.
In addition to this, in order to completely verify the operation of the SoC, it is often necessary to provide external devices to test the peripherals of the SoC, e.g., the communication connections of the SoC for communicating with devices external to the SoC. Thus, it then becomes necessary, in a simulation environment, to generate models of these external devices that may be integrated with the simulation of the SoC itself. These additional models represent additional difficulty, time and monetary cost, with regard to building and debugging these models, to simulate the required devices and to analyze the results of the simulation.
To avoid having to generate models of external devices, some simulations have the peripherals of the SoC wrapped, i.e. the SoC's inputs are tied to its outputs. Alternatively, two similar unverified device models may have their inputs and outputs tied to each other. In both cases, there is no ability to absolutely verify and debug the SoC since both input and output are associated with unverified device models and it is not possible to determine where exactly the error, if any, lies.
Often, models of external devices are available from third party vendors of these external devices which may be integrated with the test application for testing the SoC. However, even with these already established models, much effort is necessary to make the models compatible with the existing simulation environment.
Moreover, even if third party developed models of external devices are used to verify the operation of a SoC, it is still necessary to create and verify checker programs for checking the data generated by these external device models. That is, the third party developed models only provide a mechanism for simulating the initiation of transactions with the SoC and the receiving of results data from the SoC. They do not provide any means for checking the validity of the results data received. Thus, additional checking software must be developed for determining whether the generated results data indicates proper operation of the SoC or not.
All of these factors lead to a problem in that the time required to test the model of the external devices in the simulation environment may exceed the test time for the SoC that is actually being verified. Thus, it can be appreciated from the foregoing that verification of an SoC represents a substantial investment in time and money, due to the necessity of developing and executing software for performing the numerous test cases required to fully exercise the SoC design.